DIMM and Processor Physical Layout

The physical layout of the DIMMs and processor(s) is shown in the following figure. When viewing the server from the front, processor 0 (P0) is on the left.

Figure showing the AMD DIMM and processor layout.

Each processor, P0 and P1, has twelve DIMM slots (D0-D11), six on each processor side. Each DIMM slot supports a single memory channel, for total of twelve DDR5 memory channels per processor (0-11).

Table 9-1 Memory Channels and DIMM Slots for P0 and P1

Memory Channel	DIMM Slot
0	D3
1	D1
2	D0
3	D5
4	D4
5	D2
6	D8
7	D10
8	D11
9	D6
10	D7
11	D9

Note:

In single-processor systems, the DIMM slots associated with processor 1 (P1) are nonfunctional and should not be populated with DIMMs.